1. Field of the Invention
The present invention relates to semiconductor device fabrication involving dual damascene processes and structures.
2. Description of the Related Art
In semiconductor device fabrication, damascene refers to interconnect lines provided in trenches of a dielectric layer. A damascene structure in the prior art is shown in FIG. 1. Damascene structure 5 includes trench 4 which is formed in dielectric layer 2 using conventional patterning and etching techniques. A hole or via 3 is formed through dielectric layer 2 to connect trench 4 and the underlying metallization layer 1. In a damascene process, via 3 and trench 4 are filled with conductive material thereby making an electrical connection between trench 4 and metal layer 1. Excess conductive material is subsequently removed using chemical mechanical planarization (CMP) or a planarization etch back step. A damascene process wherein the trench and vias are formed before filling the resultant structure with conductive material is referred to as a dual-damascene process.
Another dual-damascene process in the prior art is now described. As shown in FIG. 2, silicon nitride (SiN) layer 7 is deposited on top of copper layer 6 to seal copper layer 6. Dielectric layer 8 is then deposited on top of SiN layer 7. Using conventional patterning techniques, resist 9 is formed over dielectric layer 8 to define a hole or via 10. Resist 9 is also referred to as a via mask.
FIG. 3 depicts the structure of FIG. 2 after via 10 is formed by etching dielectric layer 8 and removing resist 9.
As shown in FIG. 4, via 10 is filled with spin-on organic bottom anti-reflective layer (BARC) 11 to prevent etching of SiN layer 7 through via 10 during formation of the damascene trench in later fabrication steps. Resist 12, also referred to as a damascene trench mask, is patterned over BARC 11 to define the damascene trench.
FIG. 5 depicts the structure of FIG. 4 after BARC 11 is etched. FIG. 6 shows the structure of FIG. 5 after trench 13 is formed by etching dielectric layer 8.
After resist 12 and BARC 11 are removed, a portion of SiN layer 7 defined by via 10 is then etched to provide a connection between trench 13 and copper layer 6 resulting in the damascene structure shown in FIG. 7.
In the above-described process, it is difficult to fill via 10 with a void-free BARC. When voids are present in the BARC, as shown in FIG. 8, the etchant used on dielectric layer 8 to form trench 13 can etch through BARC 11, SiN layer 7, and copper layer 6 thereby rendering the semiconductor device defective.
From the foregoing, there is a clear need for a dual-damascene process that does not require a BARC fill. Further, there is a need for a dual-damascene process that requires a minimum of processing steps thereby improving manufacturing efficiency, manufacturing yield, and device reliability.